Chip giant Intel Corp. claims that it has pushed 193nm immersion lithography down to 15nm—at least in the lab.
The disclosure is further evidence that 193nm immersion—with some form of a double-patterning technique—can scale much further than previously thought. It also means that extreme ultraviolet (EUV) lithography could get pushed out—again.
So far, EUV has demonstrated the ability to print images down to 24nm or so. The industry hopes to insert EUV at the 16nm node.
Today, Intel is using ''dry'' 193nm lithography for production at the 45nm node. For the company's 32-nm process, which will go into production by year's end, Intel plans to use its first immersion tools. As reported, it plans to use 193nm immersion scanners from one vendor: Nikon Corp.
In the practical logic world, today's 193nm immersion scanners in a single exposure environment is expected to hit the wall at 35nm, said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of Components Research at Intel.
At that point, the technology begins to ''fall off the cliff,'' Mayberry said.
Like the 45-nm node, Intel plans to implement a form of phase-shift mask technology. That technology, which was described as crossbar patterns, will also enable its 32nm designs.
Then, at the 22nm node, Intel is planning to insert 193nm immersion with a double-patterning scheme. The company is also talking about using computation lithography.
In any case, there are various double-patterning schemes vying for dominance in the market. The major types include litho-etch-litho-etch, litho-freeze-litho-etch, and the sidewall spacer approach, also called SADP.
Intel may—or may not—use multiple double-patterning technologies. ''It depends on the layer,'' Mayberry said.
He said that Intel has pushed 193nm immersion with double-patterning down to 15nm. This is still in the R&D phase; the scanners have only been able to print lines and spaces—and not actual chip features.
Instead of 193nm immersion, Intel would rather use EUV for the 16-nm node. At this point, EUV is still not ready for prime time, as the alpha tools can only print lines and spaces ''down to 24-nm,'' he said. As previously reported, EUV suffers from the lack of power sources, resists and defect free masks.
The disclosure is further evidence that 193nm immersion—with some form of a double-patterning technique—can scale much further than previously thought. It also means that extreme ultraviolet (EUV) lithography could get pushed out—again.
So far, EUV has demonstrated the ability to print images down to 24nm or so. The industry hopes to insert EUV at the 16nm node.
Today, Intel is using ''dry'' 193nm lithography for production at the 45nm node. For the company's 32-nm process, which will go into production by year's end, Intel plans to use its first immersion tools. As reported, it plans to use 193nm immersion scanners from one vendor: Nikon Corp.
In the practical logic world, today's 193nm immersion scanners in a single exposure environment is expected to hit the wall at 35nm, said Mike Mayberry, vice president of the Technology and Manufacturing Group and director of Components Research at Intel.
At that point, the technology begins to ''fall off the cliff,'' Mayberry said.
Like the 45-nm node, Intel plans to implement a form of phase-shift mask technology. That technology, which was described as crossbar patterns, will also enable its 32nm designs.
Then, at the 22nm node, Intel is planning to insert 193nm immersion with a double-patterning scheme. The company is also talking about using computation lithography.
In any case, there are various double-patterning schemes vying for dominance in the market. The major types include litho-etch-litho-etch, litho-freeze-litho-etch, and the sidewall spacer approach, also called SADP.
Intel may—or may not—use multiple double-patterning technologies. ''It depends on the layer,'' Mayberry said.
He said that Intel has pushed 193nm immersion with double-patterning down to 15nm. This is still in the R&D phase; the scanners have only been able to print lines and spaces—and not actual chip features.
Instead of 193nm immersion, Intel would rather use EUV for the 16-nm node. At this point, EUV is still not ready for prime time, as the alpha tools can only print lines and spaces ''down to 24-nm,'' he said. As previously reported, EUV suffers from the lack of power sources, resists and defect free masks.
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